The replacement of doped, polycrystalline silicon structures as gate and interconnection material in very high speed integrated circuits (VHSIC) with other materials having lower sheet resistivity and, therefore, increased speed, is of substantial interest in the electronics industry. A material which has been used in such devices is a bi-layer structure composed of a refractory metal silicide overlying a layer of doped polycrystalline silicon, commonly referred to as a "polycide" structure.
A major problem associated with polycide structures is that it is difficult to etch a layer of polycide material to very fine dimensions, i.e. a micrometer or less, when it overlies vertical steps in substrate topography without the formation of conductive residues called "stringers". Stringers occur at the base of vertical steps and are difficult to eliminate, even with extended overetching. If they are not removed, they will short out a device incorporating the structure. The degree of overetching required to remove stringers often causes other problems, such as erosion of the resist with loss of linewidth definition, etching of underlying gate oxide which is exposed to the plasma during overetching, and undercutting of one or both layers of the structure. It will be appreciated that these problems become more critical as linewidths and the thickness of gate oxide decrease.
In accordance with this invention, a process has been found to provide fine dimension lines of polycide overlying vertical steps without any of the disadvantages of the prior art.